One or more embodiments of the present invention relates generally to integrated circuits, and more particularly to a semiconductor structure having an air-gap region and a method of manufacturing the same.
Semiconductor manufacturing process is typically separated into two major stages: a front-end process stage and a back-end-of-line (BEOL) process stage. The front-end process refers to the formation of electric devices, such as transistors, and/or electric components, such as resistors and capacitors, on a semiconductor substrate. On the other hand, the back-end-of-line process refers to the formation of metal interconnections between various electric devices and electric components in order to implement a circuitry as designed. Usually, layers of the metal interconnections are insulated by insulating dielectric materials, such as silicon oxide or silicate glass.
As a rule, when the density of structures and electric components on an integrated chip (IC) increases and sizes of the structures and electric components decrease, parasitic capacitances between conductive elements increase. These increased parasitic capacitances further impact transmission of electric signals in the IC by increasing power consumption and resistive-capacitive (RC) time constants. To ease the above-mentioned effects, metals with lower resistance, such as copper, are used to form the metal interconnections. Low dielectric constant (low-k) materials, which have dielectric constants lower than that of silicon oxide or silicate glass, have been developed and utilized as fillers disposed between the conductive elements. In addition to using low-k materials, pores are often formed within the fillers to further decrease the effective dielectric constant (k) value because air has a dielectric constant very close to vacuum, i.e. slightly above 1.
A variation of this porous material concept is to form air gaps within dielectric fillers in order to further reduce the effective dielectric constant value of the semiconductor structure. However, air gaps tend to raise concerns regarding electric or structural integrities of the IC, such as malfunction of the IC due to a later-formed via plug inadvertently landing on one of the air gaps, or delimitation or cracking of the IC due to pressures it suffers during a subsequent bonding or packaging process. The usage of air gaps may also cause other concerns such as thermal conductivity issues and etch-stop layer buckling.